iverilog stable port information

Package: iverilog
# Remember to fix Source line when upgrading past 0.9:
Version: 0.9.5
Revision: 1
Source: ftp://ftp.icarus.com/pub/eda/verilog/v0.9/verilog-%v.tar.gz
Source-MD5: 3eaeafbb8f0f36765676ab1aaa0fe330

Depends: readline5-shlibs, bzip2-shlibs
Provides: verilog
Conflicts: iverilog-snapshot
Replaces: iverilog-snapshot

# bison from Xcode 1.5+Nov2004 (ver. 1.2.8) works, but some versions from
# Fink (1.875 and later, but not including 2.0) break the build.
#
# Ghostscript is needed for ps2pdf (which isn't being used?)
BuildDepends: fink (>= 0.30.0), gperf, readline5, libncurses5, bison (>= 2.0), bzip2-dev

# Bug list:
#
# Needs testing/patch:
# * math.c shift overflow

DocFiles: <<
BUGS.txt COPYING QUICK_START.txt README.txt
attributes.txt cadpli/cadpli.txt glossary.txt ieee1364-notes.txt
ivl_target.txt ivlpp/ivlpp.txt lpm.txt macosx.txt
netlist.txt swift.txt t-dll.txt
tgt-fpga/fpga.txt tgt-vvp/README.txt:README.tgt-vvp.txt va_math.txt vpi.txt
vvp/README.txt:README.vvp.txt vvp/debug.txt vvp/opcodes.txt
vvp/vpi.txt:vpi-within-vvp.txt vvp/vthread.txt
xilinx-hint.txt
<<

# DocFiles found with: 'find . -name "*.txt"'
# Additional DocFiles: COPYING
# Ignored DocFiles: INSTALL cygwin.txt mingw.txt solaris/*

ConfigureParams: --mandir=%p/share/man --disable-visibility

GCC: 4.2

CompileScript: <<
#! /bin/sh -ev
### For G3/G4:
PPC_OPT="-O3 -mcpu=750 -mtune=7400"

### For G4:
# PPC_OPT="-O3 -mcpu=7400"

### For G5: (untested)
# PPC_OPT="-O3 -mcpu=G5"

DFLT_OPT="-O3"

case "%m" in
powerpc) CFLAGS="$CFLAGS $PPC_OPT" CXXFLAGS="$CXXFLAGS $PPC_OPT" ./configure %c ;;
*) CFLAGS="$CFLAGS $DFLT_OPT" CXXFLAGS="$CXXFLAGS $DFLT_OPT" ./configure %c ;;
esac

gcc --version
g++ --version

make
<<

InstallScript: <<
make install prefix=%i mandir=%i/share/man
install -d -m 755 %i/share/doc/%n/examples/vvp
install -c -p -m 644 examples/* %i/share/doc/%n/examples
install -c -p -m 644 vvp/examples/* %i/share/doc/%n/examples/vvp
ranlib %i/lib/lib*.a
<<

Description: Icarus Verilog

DescDetail: <<
Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including XNF and EDIF netlists for synthesis,
and waveform files from simulation. It strives to be true to the
IEEE-1364 standard.

A testbench is available at http://sourceforge.net/projects/ivtest

This package provides the latest stable release. If you need synthesis, you may
want to stick with the 0.8.x series in the 'iverilog08' package.

You may have both this package and iverilog08 installed at the same time.
<<

DescPort: <<
Instructions from macos.txt were followed, adapting them for the
Fink way of doing things.
<<

DescPackaging: <<
SetCXXFLAGS is used because CPPFLAGS does not appear to be honored (this
problem manifests itself as an inability to find readline/readline.h).
<<

License: GPL
Homepage: http://www.icarus.com/eda/verilog/
Maintainer: Charles Lepple